The invention relates to a serial memory, comprising a series of memory cells, data input means, data output means, control signal input means, clock signal input means and serial address input means sharing a particular terminal with said control signal input means.
A memory of this kind is known from U.S. Pat. No. 4,159,541.
The memory described therein has only four terminals; this appears to be an absolute minimum, but such a small number reduces the flexibility; for example, all input and output data, in addition to address signals and mode-control signals, must pass through a single terminal. Furthermore, the known memory uses CCD-technology which is energy-inefficient.